SELSE 2014 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design and failures in memories account for a significant fraction of costly product returns. The SELSE workshop provides a forum for discussing current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):

Technology trends and the impact on error rates.
New error mitigation techniques.
Characterizing the overhead and design complexity of error mitigation techniques.
Case studies describing the tradeoffs analysis for reliable systems.
Experimental silicon failure data.
System-level models: derating factors and validation of error models.
Error handling protocols (higher-level protocols for robust system design).

Submissions

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Additional information and guidelines for submission are available at http://www.selse.org. Submissions should be in PDF following IEEE two-column conference proceedings format that does not exceed four printed pages. Final papers may be up to six pages in length. Papers are not made available through IEEE and authors retain the copyright of their work.

Authors may optionally choose to make their final papers and/or presentations available online at the workshop web site.

Key Dates

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Abstract submission deadline: December 13, 2013
Full paper submission deadline: December 20, 2013
Notification of acceptance: February 4, 2014
Camera-ready papers: February 28, 2014

Additional Information

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Additional information and guidelines for submission are available at http://www.selse.org.

Committees

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Organizing Committee

General chairs:
Vilas Sridharan, AMD
Sarah Michalak, LANL

Program chairs:
Adrian Evans, iROC Technologies
Dimitris Gizopoulos, University of Athens

Finance chairs:
Dan Alexandrescu, iROC Technologies
Naveen Muralimanohar, HP

Local arrangements chair:
Helia Naeimi, Intel

Publicity chairs:
William H. Robinson, Vanderbilt University
Yanos Sazeides, University of Cyprus
Paolo Rech, UFRGS

Proceedings chair:
Mehdi Tahoori, Karlsruhe Institute of Technology

Webmaster:
Marios Kleanthous, Mesoyios College

For more information, visit us on the web at: http://www.selse.org

The IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 2014) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).